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Advanced
64Mb Low Power DDR SDRAM
Document Title
2M x 32 bit Low Power DDR SDRAM ( RMLD232UAW-7E ) Specification
Revision History
Revision No. 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 History Initial Draft Advanced spec. release AC/DC Values are modified. Wafer spec & PAD allocations are atteahed. PAD coordinates are not fixed (TBD). Pad allocation changed (NC Pad added to right bottom) AC (tDSS,tDSH) spec items are added. DC(Icc0,Icc2NS,Icc4R,Icc4W) spec value changed. PAD coordinates updated. PAD allocation changed. (BA0,BA1) tDS & tDH value changed. (@DDR266 : 0.8n -> 0.9n) tAC(CL=3), tDQSCK, tHZ value changed. (6.0n -> 7.0n) TCSR ICC6 Values updated. Draft Date Apr. 12 , 2006 Jul. 21 , 2006 Sep. 2 , 2006 Sep. 21 , 2006 Nov. 14 , 2006 Dec. 6 , 2006 Dec. 19 , 2006 Nov. 27 , 2007 Remark Draft Advanced Advanced Advanced Advanced Advanced Advanced Preliminary
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
Emerging Memory & Logic Solutions Inc.
Zip Code : 690-717
The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office.
1
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM 2M x 32 Low Power DDR SDRAM
Features
1.8V power supply, 1.8V I/O power Double-data-rate architecture; two data transfers per clock cycle Bidirectional data strobe(DQS) Four banks operation Differential clock inputs(CK and CK) MRS cycle with address key programs - CAS Latency ( 3 ) - Burst Length ( 2, 4, 8, 16 ) - Burst Type (Sequential & Interleave) - Partial Self Refresh Type ( Full, 1/2, 1/4 array ) - Internal Temperature Compensated Self Refresh - Driver strength ( 1, 1/2, 1/4, 1/8 ) Deep Power Down Mode All inputs except data & DM are sampled at the positive going edge of the system clock(CK). Data I/O transactions on both edges of data strobe, DM for masking. Edge aligned data output, center aligned data input. No DLL; CK to DQS is not synchronized. DM0 - DM3 for write masking only. 15.6 auto refresh duty cycle.

Opreating Frequency
DDR266 Speed @CL2 Speed @CL3 *CL : CAS Latency 83 133 DDR222 66 111
Column Address Configuration
Organization
Row Address A0 ~ A10
Column Address A0-A7
2M
32
DM is internally loaded to match DQ and DQS identically.
General Wafer Specifications
Process Technology : 0.125um Trench DRAM Process Wafer thickness : 725 +/- 25um Wafer Diameter : 8-inch
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64Mb Low Power DDR SDRAM
Input/Output Function Description
SYMBOL CK, CK TYPE Input DESCRIPTION Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Internal clock signals are derived from CK/CK. Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWERDOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for all funtions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE , are disabled during power-down and self refresh mode which are contrived for low standby power consumption. Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. Command Inputs : RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS loading. For the x32, DM0 corresponds to the data on DQ0-DQ7 ; DM1 corresponds to the data on DQ8-DQ15 ;DM2 corresponds to the data on DQ16-DQ23 ; DM3 corresponds to the data on DQ24-DQ31 . Bank Address Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines wherther the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0,BA1. The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 determines which mode register( mode register or extended mode register ) is loaded during the MODE REGISTER SET command. Data Input/Output : Data bus Data Strobe : Output with read data, input with write data. Edge-aligned with read data, centered in write data. It is used to fetch write data. For the x32, DQS0 corresponds to the data on DQ0-DQ7 ; DQS1 corresponds to the data on DQ8-DQ15 ;DQS2 corresponds to the data on DQ16-DQ23 ; DQS3 corresponds to the data on DQ24-DQ31. No Connect : No internal electrical connection is present. DQ Power Supply : 1.7V to 1.95V. DQ Ground. Power Supply : 1.7V to 1.95V. Ground.
CKE
Input
CS
Input
RAS, CAS, WE
*1DM0,
Input Input
DM1 DM2, DM3
BA0,BA1 A [n : 0]
Input Input
*1 *1
DQ
I/O I/O
DQS0, DQS1 DQS2, DQS3
NC VDDQ VSSQ VDD VSS
Supply Supply Supply Supply
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Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Functional Description
CKEH DEEP POWER DOWN PARTIAL SELF REFRESH
POWER APPLIED
POWER ON
PRECHARGE ALL BANKS
DEEP POWER DOWN
SELF REFRESH
REFS REFSX
EMRS
MRS
MRS
IDLE ALL BANKS PRECHARGED
REFA
AUTO REFRESH
CKEL CKEH ACT POWER DOWN
POWER DOWN
CKEH CKEL WRITE READA READ READ ROW ACTIVE BURST STOP READ
WRITEA WRITE
WRITEA READA
READA
WRITEA PRE
PRE PRE
READA
PRE
PRECHARGE PREALL Automatic Sequence Command Sequence
Figure.1 State diagram
4 Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Power Up Sequence for Low Power DDR SDRAM
CK CK CKE CS RAS CAS ADDR BA0 BA1 A10/AP DQ WE DQS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
High
Key
Key
RAa
RAa
Hi-Z
Hi-Z
Hi-Z tRP Precharge (All Bank) Auto Refresh tARFC
Hi-Z
tARFC Auto Refresh Normal MRS Row Active (A-Bank)
Extended MRS
NOTE : 1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined. -Apply VDD before or at the same time as VDDQ. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200 . 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. 6. Issue a extended mode register set command to define PASR or DS operating type of the device after normal MRS.
: Don't Care
EMRS cycle is not mandatory and the EMRS command needs to be issued only when either PASR or DS is used. The default state without EMRS command issued is half driver strength, and Full array refreshed. The device is now ready for the operation selected by EMRS. For operating with PASR or DS, set PASR of DS mode in EMRS setting stage. In order to adjust another mode in the state of PASR or DS mode, additional EMRS set is required but power up sequence is not needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.
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64Mb Low Power DDR SDRAM Mode Register Definition
Mode Register Set (MRS)
The mode register is designed to support the various operating modes of DDR SDRAM. It includes CAS latency, addressing mode, burst length, test mode and vendor specific options to make DDR SDRAM useful for variety of applications. The default value of the mode register is not defined, therefore the mode register must be written in the power up sequence of DDR SDRAM. The mode register is written by asserting low on CS, RAS, CAS and WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A0~A10 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Two clock cycles are required to complete the write operation in the mode register. Even if the power-up sequence is finished and some read or write operations is executed afterward, the mode register contents can be changed with the same command and four clock cycles. This command must be issued only when all banks are in the idle state. If mode register is changed, extended mode register automatically is reset and come into default state. So extended mode register must be set again. The mode register is divided into various fields depending on funtionality. The burst length uses A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 ~ A10 are used for test mode. BA0 and BA1 must be set to low for normal DDR SDRAM operation.
BA1
BA0
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
0
0
0
0
0
0
CAS Latency
BT
Burst Length
Mode Register
A3 A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CAS Latency Reserve Reserve 2 3 Reserve Reserve Reserve Reserve 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1
Burst Type Sequential Interleave
Burst Length
A2 A1 A0 Burst Type Sequential Reserve 2 4 8 16 Reserve Reserve Reserve Interleave Reserve 2 4 8 16 Reserve Reserve Reserve
Figure.2 Mode Register Set
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64Mb Low Power DDR SDRAM
Burst address ordering for burst length
Burst Length 2 Starting Address (A3, A2, A1, A0) xxx0 xxx1 xx00 4 xx01 xx10 xx11 x000 x001 x010 8 x011 x100 x101 x110 x111 0000 0001 0010 0011 0100 0101 0110 16 0111 1000 1001 1010 1011 1100 1101 1110 1111 Sequential Mode 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 Interleave Mode 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 2, 3, 0, 1, 6, 7, 4, 5, 10, 11, 8, 9, 14, 15, 12, 13 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 4, 5, 6, 7, 0, 1, 2, 3, 12, 13, 14, 15, 8, 9, 10, 11 5, 4, 7, 6, 1, 0, 3, 2, 13, 12, 15, 14, 9, 8, 11, 10 6, 7, 4, 5, 2, 3, 0, 1, 14, 15, 12, 13, 10, 11, 8, 9 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7 9, 8, 11, 10, 13, 12, 15, 14, 1, 0, 3, 2, 5, 4, 7, 6 10, 11, 8, 9, 14, 15, 12, 13, 2, 3, 0, 1, 6, 7, 4, 5 11, 10, 9, 8, 15, 14, 13, 12, 3, 2, 1, 0, 7, 6, 5, 4 12, 13, 14, 15, 8, 9, 10, 11, 4, 5, 6, 7, 0, 1, 2, 3 13, 12, 15, 14, 9, 8, 11, 10, 5, 4, 7, 6, 1, 0, 3, 2 14, 15, 12, 13, 10, 11, 8, 9, 6, 7, 4, 5, 2, 3, 0, 1 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
7
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Extended Mode Register Set (EMRS)
The extended mode register is designed to support partial array self refresh or driver strength. EMRS cycle is not mandatory and the EMRS command needs to be issued only when either PASR or DS is used. The defalt state without EMRS command issued is +85 , all 4 banks refreshed and the half size of driver strength. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA1, low on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0 ~ A10 in the same cycle as CS, RAS, CAS and WE going low is written in the extended mode register. Two clock cycles are required to complete the write operation in the extended mode register. Even if the power-up sequence is finished and some read or write operations is executed afterward, the mode register contents can be changed with the same command and four clock cycles. But this command must be issued only when all banks are in the idle state. A0 ~ A2 are used for partial array self refresh and A5 ~ A6 are used for driver strength. "High" on BA1 and "Low" on BA0 are used for EMRS. All the other address pins except A0, A1, A2, A5, A6, BA1, BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.
Extended MRS for PASR(Partial Array Self Refresh) & DS & TCSR(Internal Temperature Compensated Self Refresh)
BA1 BA0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
1 1
0 1
1/4 1/8
8

1
0
0
0
0
0
DS
0
0
PASR
Mode Register
Driver Strength A6 0 0 A5 0 1 Driver Strength Full 1/2 (default)
Inernal TCSR Self refresh cycle is controlled automatically by internal temperature sensor and control circuit according to the four temperature ; Max 15 , Max 45 , Max 70 , Max 85 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1
PASR Size of Refreshed Array Four Banks (default) Two Banks (Bank 0,1) One Bank (Bank 0) Reserved Reserved Reserved Reserved Reserved
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Internal Temperature Compensated Self Refresh (TCSR)
Note : 1. In order to save power consumption, Low Power DDR SDRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically according to the four temperature range ; Max. 15 , Max. 45 , Max. 70 , Max. 85 . 2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.

Temperature Range Max. 15
Self Refresh Current (Icc6) Full Array 210 1/2 Array 160 170 180 190 1/4 Array 130 135 140 150
Unit
Max. 45
Max. 70
230 250
Max. 85
Partial Array Self Refresh (PASR)
Note : 1. In order to save power consumption, Mobile DDR SDRAM includes PASR option. 2. Low Power DDR SDRAM supports three kinds of PASR in self refresh mode; Four banks, Two banks, One bank.
BA1=0 BA1=0 BA0=0 BA0=1
BA1=0 BA1=0 BA0=0 BA0=1
BA1=0 BA1=0 BA0=0 BA0=1 BA1=1 BA1=1 BA0=0 BA0=1
- One Bank (Bank0)
BA1=1 BA1=1 BA0=0 BA0=1
- Four Bank
BA1=1 BA1=1 BA0=0 BA0=1
- Two Bank (Bank0,1)
Partial Self Refresh Area
Figure.3 EMRS code and TCSR, PASR
9
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Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Precharge
The precharge command is used to precharge or close a bank that has been activated. The precharge command is issued when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank respectively or all banks simultaneously. The bank select addresses(BA0, BA1) are used to define which bank is precharged when the command is initiated. For write cycle, tWR(min.) must be satisfied until the precharge command can be issued. After tRP from the precharge, an active command to the same bank can be initiated.
Bank selection for precharge by Bank Address bits
A10/AP 0 0 0 0 1 BA1 0 0 1 1 X BA0 0 1 0 1 X Precharge Bank A Only Bank B Only Bank C Only Bank D Only All Banks
No Operation(NOP) & Device Deselect
The device should be deselected by deactivating the CS signal. In this mode DDR SDRAM should ignore all the control inputs. The DDR SDRAMs are put in NOP mode when CS is active and by deactivating RAS, CAS and WE. Both Device Deselect and NOP command can not affect operation already in progress. So even if the device is deselected or NOP command is issued under operation, operation will be complete.
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Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Row Active
The Bank Activation cimmand is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock(CK). The DDR SDRAM has four independent banks, so two Bank Select addresses(BA0, BA1) are required. The Bank Activation command must be applied before any Read or Write operation is executed. The delay from the Bank Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time(tRCD min). Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between interleaved Bank Activation comands(Bank A to Bank B and vice versa) is the Bank to Bank delay time(tRRD min).
Bank Activation Command Cycle
CK CK Address
Bank A Row Addr. RAS-CAS delay(tRCD) Bank A Col. Addr. Bank B Row Addr. Bank A Row Addr.
0
1
2
3
4
5
Tn
Tn+1
RAS-RAS delay time(tRRD) Write A with Auto Precharge NOP Bank B Activate NOP Bank A Activate
Command
Bank A Activate
NOP
NOP
ROW Cycle Time(tRC)
Figure.4 Bank activation command cycle timing
: Don't Care
Read Bank
This command is used after the row activate command to initiate the burst read of data. The read command is initiated by activating CS, CAS, and deassertig WE, RAS at the same clock sampling(rising) edge as described in the command truth table. The length of the burst and the CAS latency time will be determined by the values programmed during the MRS cycle.
Write Bank
This command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating RAS, CS, WE, and deassertig RAS at the same clock sampling(rising) edge as described in the command truth table. The length of the burst will be determined by the values programmed during the MRS cycle.
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64Mb Low Power DDR SDRAM
Essential Functionality for DDR SDRAM
The essential functionality that is required for the DDR SDRAM device is described in this chapter
Burst Read Operation
Burst Read operation in DDR SDRAM is in the same manner as the SDRAM such that the burst read command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock(CK) after tRCD from the bank activation. The address inputs (A0~A9) determine the starting address for the Burst. The Mode Register sets type of burst(Sequential or interleave) and burst length(2, 4, 8, 16). The first output data is available after the CAS Latency from the READ command, and the consecutive data are presented on the falling and rising edge of Data Strobe(DQS) adopted by DDR SDRAM until the burst length is completed.
< Burst Length=4, CAS Latency=3 >
CK CK Command DQS DQs CAS Latency=3
READ A NOP NOP tRPRE tAC NOP NOP tRPST Postamble
Dout 0 Dout 1 Dout 2 Dout 3
0
1
2
3
4
5
6
7
8
NOP
NOP
NOP
NOP
Preambel
Figure.5 Burst read operation timing
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Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Burst Write Operation
The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock(CK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst write cycle. The first data of a burst write cycle must be applied on the DQ pins tDS(Data-in setup time) prior to data strobe edge enabled after tDQSS from the rising edge of the clock(CK) that the write command is issued. The remaining data inputs must be supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any additional data supplied to the DQ pins will be ignored.
< Burst Length=4 >
CK CK Command DQS DQs
NOP WRITEA NOP WRITEB
*1
0
1
*1
2
3
4
5
6
7
8
NOP
NOP
NOP
NOP
NOP
tDQSSmax tWPRES*1
Din 0 Din 1 Din 2 Din 3 Din 0 Din 1 Din 2 Din 3
Figure.6 Burst write operation timing
1. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS.
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64Mb Low Power DDR SDRAM
Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point the data from the interrupting Read command appears. Read to Read interval is minimum 1 Clock.
< Burst Length=4, CAS Latency=3 >
CK CK Command DQS DQs CAS Latency=3
READ A READ B NOP tAC tRPRE Preamble
Dout A0 Dout A1 Dout B0 Dout B1 Dout B2 Dout B3
0
1
2
3
4
5
6
7
8
NOP
NOP
NOP
NOP
NOP
NOP
Figure.7 Read interrupted by a read timing
Read Interrupted by a Write & Burst Stop
To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O bus by placing the DQs(Output drivers) in a high impedance state. To insure the DQs are tri-stated one cycle before the beginning of the write operation, Burst stop command must be applied at least 2 clock cycles for CL=2 and at least 3 clock cycles for CL=3 before the Write command.
< Burst Length=4, CAS Latency=3 >
CK CK Command DQS DQs CAS Latency=3
READ Burst Stop NOP tRPRE Preamble tAC
Dout 0 Dout 1 Din 0 Din 1 Din 2 Din 3
0
1
2
3
4
5
6
7
8
NOP
NOP
WRITE
NOP
NOP
tDQSS tWPRES tWPREH
Figure.8 Read interrupted by a Write and burst stop timing
The following functionality establishes how a Write command may interrupt a Read burst. 1. For Write commands interrupting a Read burst, a Burst Terminate command is required to stop the read burst and tristate the DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum delay to a Write command =RU(CL) [CL is the CAS Latency and RU means round up to the nearest integer]. 2. It is illegal for a Write command to interrupt a Read with autoprecharge command.
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64Mb Low Power DDR SDRAM
Read Interrupted by a Precharge
A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency.
< Burst Length=8, CAS Latency=3 >
CK CK Command DQS DQs CAS Latency=3
READ
0
1tCK
1
2
3
4
5
6
7
8
Precharge
NOP tRPRE tAC
NOP
NOP
NOP
NOP
NOP
NOP
Dout 0 Dout 1 Dout 2 Dout 3 Dout 4 Dout 5 Dout 6 Dout 7 Interrupted by precharge
Figure.9 Read interrupted by a precharge timing
when a burst Read command is issued to a DDR SDRAM, a precharge command may be issued to the same bank before the Read burst is complete. The following functionality determines when a Precharge command may be given during a Read burst and when a new Bank Activate command may be issued to the same bank. 1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank Activate command may be issued to the same bank after tRP (RAS Precharge time). 2. when a Precharge command interrupts a Read burst operation, the precharge command may be given on the rising clock edge which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last data word has been output, the output buffers are tristated, A new Bank Activate command may be issued to the same bank after tRP. 3. For a Read with autoprecharge command, a new Bank Activate command may be issued to the same bank after tRP where tRP begins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. During Read with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above. 4. For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between a Precharge command and a new Bank Activate command to the same bank equals tRP/tCK(where tCK is the clock cycle time) with the result rounded up to the nearest integer number of clock cycles. (Note that rounding to x .5 is not possible since the Precharge and Bank Activate commands can only be given on a rising clock edge). In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Read with autoprecharge commands where tRAS(min) must still be satisfied such that a Read with autoprecharge command has the same timing as a Read command followed by the earliest possible Precharge command which does not interrupt the burst.
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Advanced
64Mb Low Power DDR SDRAM
Write Interrupted by a Write
A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.
< Burst Length=4 >
CK CK Command DQS DQs
NOP
0
1
1tCK WRITE A
2
3
4
5
6
7
8
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
Din A0 Din A1 Din B0 Din B1 Din B2 Din B3
Figure.10 Write interrupted by a write timing
16
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Write Interrupted by a Precharge & DM
A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column access is allowed. A write recovery time(tWR) is required from the last data to precharge command. When precharge command is asserted, any residual data from the burst write cycle must be masked by DM.
< Burst Length=8 >
CK CK Command
NOP WRITE A NOP NOP NOP NOP Precharge WRITE B NOP
0
1
2
3
4
5
6
7
8
tDQSSmax DQS Max tDQSS DQs tDQSSmin tWPRES tWPREH tWPRES tWPREH
tWR
tDQSSmax tWPRES tWPREH
Din b0 Din b1
Din a0 Din a1 Din a2 Din a3 Din a4 Din a5 Din a6 Din a7
DM DQS Min tDQSS DQs
tWR
tDQSSmin tWPRES tWPREH
Din b0 Din b1 Din b2
Din a0 Din a1 Din a2 Din a3 Din a4 Din a5 Din a6 Din a7
DM
Figure.11 Write interrupted by a precharge and DM timing
Precharge timing for Write operations in DRAMs requries enough time to allow "write recovery " which is the time required by a DRAM core to properly store a full "0" or "1" level before a Precharge operation. For DDR SDRAM, a timing parameter, tWR, is used to indicate the required amount of time between the last valid write operation and a Precharge command to the same bank. The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and the address is sampled by the input clock. Inside the SDRAM, the data path is eventually synchronized with the address path by swithing clock domains from the data strobe clock domain to the input clock domain. This makes the definition of when a precharge operation can be initiated after a write very complex since the write recovery parameter must reference only the clock domain that is used to time the internal write operation, i.e., the input clock domain. tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid data and ends on the rising clok edge that strobes in the prechrge command. 1. For the earilest possible Precharge command following a Write burst without interrupting the burst , the minimum time for write recovery is defined by tWR. 2. When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask input data during the time between the last valid write data and the rising clock edge on which the Precharge command is given. During this time, the DQS input is still required to strobe in the state of DM. The minimum time for write recovery is defined by tWR. 3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after tWR+tRP where tWR+tRP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the Bank Activate command. During write with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command without interrupting the Write burst as described in 1 above. 4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Write with autoprecharge commands where tRAS(min) must still be satisfied such that a Write with autoprecharge command has the same timing as a Write command followed by the earliest possible Precharge command which does not interrupt the burst. 5. Refer to "3.3.2 Burst write operation"
17
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Burst Stop
The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock(CK). The burst stop command has the fewest restrictions making it the easiest method to use when terminating a burst read operation before it has been completed. When the burst stop command is issued during a burst read cycle, the pair of data and DQS(Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the mode register. The burst stop command, however, is not supported during a write burst operation.
< Burst Length=4, CAS Latency=3 >
CK CK Command DQS DQs CAS Latency=3
READ A Burst Stop NOP NOP NOP NOP NOP NOP NOP
0
1
2
3
4
5
6
7
8
The burst read ends after a delay equal to the CAS latency.
Dout 0 Dout 1
Figure.12 Burst stop timing
The Burst Stop command is a mandatory feature for DDR SDRAMs. The following functionality is required: 1. The BST command may only be issued on the rising edge of the onput clock, CK. 2. BST is only a valid command during Read bursts. 3. BST during a Write burst is undefined and shall not be used. 4. BST applies to all burst lengths. 5. BST is an undefined command during Read with autoprecharge and shall not be used. 6. When terminating a burst Read command, the BST command must be issued LBST("BST Latency") clock cycles before the clock edge at which the output buffers are tristated, where LBST equals the CAS latency for read operations. 7. When the burst terminates, the DQ and DQS pins are tristated. The BST command is not byte controllable and applies to all bits in the DQ data word and the(all) DQS pin(s).
18
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
DM masking
The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle, not read cycle. When the data mask is activated (DM high) during write operation, DDR SDRAM does not accept the corresponding data.(DM to data-mask latency is zero). DM must be issued at the rising or falling edge of data strobe.
< Burst Length=8 >
CK CK Command DQS tWPRES tWPREH DQs
Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7
0
1
2
3
4
5
6
7
8
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSSmax
DM masked by DM=H
Figure.13 DM masking timing
19
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Read with Auto Precharge
If a read with auto-precharge command is issued, the DDR SDRAM automatically enters the precharge operation BL/2 clock later from a read with auto-precharge command when tRAS(min) is satisfied. If not, the start point of precharge operation will be delayed until tRAS(min) is satisfied. Once the precharge operation has started, the bank cannot be reactivated and the new command can not be asserted until the precharge time(tRP) has been satisfied.
< Burst Length=4, CAS Latency=3 >
CK CK Command DQS
BANK A ACTIVE NOP NOP NOP
Auto Precharge
0
1
2
3
4
5
6
7
8
9
10
11
READ A
NOP
NOP
NOP tRP
NOP
NOP
NOP
NOP
*Bank can be reactivated at completion of tRP
DQs CAS Latency=3
tRAS(min)
Auto-Precharge starts*1
Dout 0 Dout 1 Dout 2 Dout 3
Figure.14 Read with auto precharge timing
*NOTE : 1. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of other activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same bank is illegal.
20
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Write with Auto Precharge
If A10 is high when write command is issued , the write with auto-precharge function is performed. Any new command to the same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWP(min).
< Burst Length=4 >
CK CK Command BANK A
ACTIVE NOP NOP NOP
Auto Precharge
0
1
2
3
4
5
6
7
8
9
10
11
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS
*Bank can be reactivated at completion of tRP
DQs
Din 0
Din 1 Din 2 Din 3
tWR
tRP
Internal precharge starts*1
Figure.15 Write with auto precharge timing
*NOTE : 1. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of other activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same bank is illegal.
21
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Auto Refresh & Self Refresh
Auto Refresh An auto refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the rising edge of the clock(CK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of the external address pins is required once this cycle has started because of the internal address counter. When the refresh cycle has completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate command or subsequent auto refresh command must be greater than or equal to the tARFC(min).
CK CK Command CKE = High
PRE Auto Refresh CMD
tRP
tARFC(min)
Figure.16 Auto refresh timing
Self Refresh A Self Refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. Once the self Refresh command is initiated, CKE must be held low to keep the device in Self Refresh mode. After 1 clock cycle from the self refresh command, all of the external control signals including sysem clock(CK, CK) can be disabled except CKE. The clock is internally disabled during Self Refresh operation to reduce power. To exit the Self Refresh mode, supply stable clock input before returning CKE high, assert deselect or NOP command and then assert CKE high. In case that the system uses burst auto refresh during normal operation, it is recommended to use burst 8192 auto refresh cycle immediately before entering self refresh mode and after exiting in self refresh mode. On the other hand, if the system uses the distributed auto refresh, the system only has to keep the refresh duty cycle.
CK CK Command
Self Refresh Stable Clock NOP tSRFX(min) Active
CKE
tIS tIS
Figure.17 Self refresh timing
22
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Power down
The device enters power down mode when CKE Low, and it exits when CKE High. Once the power down mode is initiated, all of the receiver circuits except CK and CKE are gated off to reduce power consumption. The both bank should be in idle state prior to entering the precharge power down mode and CKE should be set high at least 1 tCK+tIS prior to Row active command. During power down mode, refresh operations cannot be performed, therefore the device cannot remain in power down mode longer than the refresh period(tREF) of the device.
0 CK CK
1
2
3
4
5
6
7
8
9
10
11
12
13
Command Precharge
Precharge power down Entry
Precharge power down Exit (NOP) tPDEX
Active
Active power down Entry
Active power down Exit
READ
CKE
tIS tIS tIS tIS
Figure.18 Power down entry and exit timing
23
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Command Truth Tabe (V=Valid, X=Don,t Care, H=Logic High, L=Logic Low)
COMMAND Register Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit CKEn-1 H H CKEn X H L H X X CS L L L H L L RAS L L H X L H CAS L L H X H L WE L H H X H H V V BA0,1 A10/AP OP CODE X A9 ~ A0 Note 1,2 3 3 3 3
L H H
X Row Address L H L H X X V X L H X Column Address (A0 ~ A7) Column Address (A0 ~ A7)
Bank Active & Row Addr. Read & Column Address Wrie & Column Address Deep Power Down Burst Stop Precharge Bank Selection All Banks Entry Exit Entry Precharge Power Down Mode Exit DM No operation (NOP) : Not defined Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable Entry Exit
4 4 4 4, 6
H H L H H
X L H X X
L L H L L H L X H L H L
H H X H L X V X X H X V X
L H X H H X V X X H X V
L L X L L X V X X H X V
V
7
5
Active Power Down
H L H
L H L
X
X
L H H
H
X X H X H X
8 9 9
X
H L
X H
1. OP Code : Operation Code. A0 ~ A10 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. 5. If A10/AP is "High" at row precharge, BA0 and BA1are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
24
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Functional Truth Table
Current State CS L L PRECHARGE STANDBY L L L L L L L L L L L L RAS H H L L L L H H H L L L L H CAS H L H H L L H L L H H L L H WE L X H L H L L H L H L H L L X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X Address Command Burst Stop READ/WRITE Active PRE/PREA Refresh MRS Burst Stop READ/READA WRITE/WRITEA Active PRE/PREA Refresh MRS Burst Stop Action ILLEGAL*2 ILLEGAL*2 Bank Active, Latch RA ILLEGAL*4 AUTO-Refresh*5 Mode Register Set*5 NOP Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge Bank Active/ILLEGAL*2 Precharge/Precharge All ILLEGAL ILLEGAL Terminate Burst Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge*3 ILLEGAL Bank Active/ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL
ACTIVE STANDBY
L
H
L
H
BA, CA, A10
READ/READA
READ
L L L L L
H L L L L
L H H L L
L H L H L
BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add
WRITE/WRITEA Active PRE/PREA Refresh MRS
25
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Functional Truth Table
Current State CS L RAS H CAS H WE L X Address Command Burst Stop ILLEGAL Terminate Burst with DM=High, Latch CA, Begin Read, Determine Auto-Precharge*3 Terminate Burst, Latch CA, Begin new Write, Determine AutoPrecharge*3 Bank Active/ILLEGAL*2 Terminate Burst with DM=High, Precharge ILLEGAL ILLEGAL ILLEGAL ILLEGAL, Different Bank is LEGAL ILLEGAL, Different Bank is LEGAL ILLEGAL, Different Bank is LEGAL ILLEGAL, Different Bank is LEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL, Different Bank is LEGAL ILLEGAL, Different Bank is LEGAL ILLEGAL, Different Bank is LEGAL ILLEGAL, Different Bank is LEGAL ILLEGAL ILLEGAL Action
L
H
L
H
BA, CA, A10
READ/READA
L WRITE L L L L L L READ with AUTO PRECHARGE*6 (READA) L L L L L L L WRITE with AUTO PRECHARGE*7 (WRITEA) L L L L L
H
L
L
BA, CA, A10
WRITE/WRITEA
L L L L H H H L L L L H H H L L L L
H H L L H L L H H L L H L L H H L L
H L H L L H L H L H L L H L H L H L
BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add
Active PRE/PREA Refresh MRS Burst Stop READ/READA WRITE/WRITEA Active PRE/PREA Refresh MRS Burst Stop READ/READA WRITE/WRITEA Active PRE/PREA Refresh MRS
26
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Functional Truth Table
Current State CS L L PRECHARGING (DURING tRP) L L L L L L ROW ACTIVATING (FROM ROW ACTIVE TO tRCD) L L L L L L WRITE RECOVERING (DURING tWR OR tCDLR) L L L L L RAS H H L L L L H H L L L L H H H L L L L CAS H L H H L L H L H H L L H L L H H L L WE L X H L H L L X H L H L L H L H L H L X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Address Command Burst Stop READ/WRITE Active PRE/PREA Refresh MRS Burst Stop READ/WRITE Active PRE/PREA Refresh MRS Burst Stop READ WRITE Active PRE/PREA Refresh MRS Active ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 NOP*4(Idle after tRP) ILLEGAL ILLEGAL ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL ILLEGAL*2 ILLEGAL*2 WRITE ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
27
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Functional Truth Table
Current State CS L L REFRESHING L L L L L L MODE REGISTER SETTING L L L L RAS H H L L L L H H L L L L CAS H L H H L L H L H H L L WE L X H L H L L X H L H L X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Address Command Burst Stop READ/WRITE Active PRE/PREA Refresh MRS Burst Stop READ/WRITE Active PRE/PREA Refresh MRS Action ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
28
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Functional Truth Table
Current State CKEn-1 L L SELFREFRESHING
*8
CKEn H H H H H L H L H L H L L L L L L X H
CS H L L L L X X X H X X L H L L L L X X
RAS X H H H L X X X X X X L X H H H L X X
CAS X H H L X X X X X X X L X H H L X X X
WE X H L X X X X X X X X H X H L X X X X
Add X X X X X X X X X X X X X X X X X X X
Action Exit Self-Refresh Exit Self-Refresh ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Self-Refresh) Exit Power Down(Idle after tPDEX) NOP(Maintain Power Down) Exit Deep Power Down *10 NOP(Maintain Deep Power Down) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State=Power Down Refer to Function Truth Table
L L L L
POWER DOWN DEEP POWER DOWN
L L L L H H H
ALL BANKS IDLE*9
H H H H L
ANY STATE other than listed above
H
ABBREVIATIONS : H=High Level, L=Low level, X=Don't Care NOTE : 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state ; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around and write recovery requirements. 4. NOP to bank precharging or in idle sate. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. 6. Refer to "Read with Auto Precharge Timing Diagram" for detailed information. 7. Refer to "Write with Auto Precharge Timing Diagram" for detailed infotmation. 8. CKE Low to High transition will re-enable CK, CK and other inputs asynchronously. A minimum setup time must be satisfied before issuing any command other than EXIT. 9. Power-Down and Self-Refresh and Deep Power Down Mode can be entered only from All Bank Idle state. 10. The Deep Power Down Mode is exited by asserting CKE high and full initialization is required after exting Deep Power Down Mode. ILLEGAL = Device operation and/or data integrity are not guaranteed.
29
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Absolute maximum ratings
Parameter Voltage on any pin relative to VSS Voltage on VDD supply realtive to VSS Voltage on VDD supply realtive to VSS Storage temperature Operatiing temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD VDDQ TSTG TA PD IOS Value -0.5 ~ 2.7 -0.5 ~ 2.7 -0.5 ~ 2.7
|
Uint V V V
-55 ~ +150
|
-25 ~ +85 1.0 50
W
NOTE : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommand operation condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Conditions & Specifications
DC Operating Conditions
| |
Recommended operating conditions (Voltage referenced to VSS=0V, TA=-25
Parameter Supply voltage(for device with a nominal VDD of 1.8V) I/O supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Output leakage current Symbol VDD VDDQ VIH(DC) VIL(DC) VOH(DC) VOL(DC) II IOZ Min 1.7 1.7 0.7 x VDDQ -0.3 0.9 x VDDQ -2 -5
to 85 Max 1.95 1.95
) Unit V V V V V V
Note 1 1 2 2
VDDQ + 0.3 0.3 x VDDQ 0.1 x VDDQ 2
IOH = -0.1
IOL = 0.1
5
NOTE : 1. Under all conditions, VDDQ must be less than or equal to VDD 2. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation.
30
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
DC CHARACTERISTICS
Parameter Operating Current (One Bank Active/Precharge current) Operating Current (One Bank Active-Read-Precharge current; Burst=4) Symbol Test Condition tRC=tRCmin; tCK=tCKmin ; CKE is HIGH; CS is HIGH between valid commands; address inputs are switching every two clock cycles; Data bus inputs are stable tRC=tRCmin; tCK=tCKmin ; CKE is HIGH; IOUT = 0 ; Address and control inputs changing once per clock cycle All banks idle, CKE is LOW; CS is HIGH, tCK=tCKmin; Address and control inputs are switching every two clock cycles; Data bus inputs are stable All banks idle, CKE is LOW; CS is HIGH, CK=LOW, CK=HIGH; address and control inputs are switching every two clock cycles; Data bus inputs are stable All banks idle, CKE is HIGH; CS is HIGH, tCK=tCKmin; Address and control inputs are switching every two clock cycles; Data bus inputs are stable All banks idle, CKE is HIGH; CS is HIGH, CK=LOW, CK=HIGH; Address and control inputs are switching every two clock cycles; Data bus inputs are stable One bank active, CKE is LOW; CS is HIGH, tCK=tCKmin; Address and control inputs switching every two clock cycles; Data bus inputs are stable One bank active, CKE is LOW; CS is HIGH, CK=LOW, CK=HIGH; Address and control inputs are switching every two clock cycles; Data bus inputs are stable One bank active, CKE is HIGH; CS is HIGH, tCK=tCKmin; Address and control inputs switching every two clock cycles; Data bus inputs are stable One bank active, CKE is HiGH; CS is HIGH, CK=LOW, CK=HIGH; Address and control inputs are switching every two clock cycles; Data bus inputs are stable One bank active; BL=4; CL=3; tCK=tCKmin; Continuous read bursts; IOUT = 0 ; Address inputs are switching; 50% data change each burst tranfer One bank active; BL=4; tCK=tCKmin; Continuous write bursts; Address inputs are switching; 50% Data change each burst transfer tRC=tRFCmin; tCK=tCKmin; burst refresh; CKE is HIGH; Address and control inputs are switching; Data businputs are stable TCSR Range
|
Recommended operating conditions (Voltage referenced to VSS = 0V, Temp = -25 to 85
)
DDR 266 DDR 222 Unit
IDD2PS
0.5
IDD2NS
10
10
IDD3P
Active Standby Current in power-down mode
5
IDD3PS
3
Operating Current (Burst Mode)
Self Refresh Current
IDD6
1 Bank Deep Power Down Current
135 10
150
IDD8 *1
Address and control inputs are stable; Data bus inputs are stable
NOTE : 1. DPD (Deep Power Down) function is an optional feature, and it will be enabled upon request. Please contact Ramsway for more information. 2. IDD specifications are tested after the device is properly intialized.
(c)
3. Input slew rate is 1V/ 4. Definitions for IDD:
. 0.1*VDDQ;

LOW is defined as VIN HIGH is defined as VIN
0.9*VDDQ;
31
Rev 0.7
CKE is LOW; tCK= tCKmin ; Extended Mode Register set to all 0's; address and control inputs are stable; Data bus inputs are stable
4 Banks 2 Banks
220 170
250 190
|
Max 45
Max 85
Refresh Current
IDD5
100
95
IDD4W
100
95
IDD4R
120
115
IDD3NS
20
15
Active Standby Current in non power-down mode (One Bank Active)
IDD3N
25
20
Precharge Standby Current in non power-down mode
IDD2N
20
15
Precharge Standby Current in power-down mode
IDD2P
0.5
IDD1
100
95
IDD0
80
75
Advanced
64Mb Low Power DDR SDRAM
STABLE is defined as inputs stable at a HIGH or LOW level; SWITCHING is defined as: -address and command: inputs changing between HIGH and LOW once per two clock cycles -data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.
AC operating Conditions & Timing Specification
Parameter/Condition Input High (Logic 1) Voltage, all inputs Input Low (Logic 0) Voltage, all inputs Input Crossing Point Voltage, CK and CK inputs Symbol VIH(AC) VIL (AC) VIX(AC) Min 0.8 x VDDQ -0.3 0.4 x VDDQ Max VDDQ + 0.3 0.2 x VDDQ 0.6 x VDDQ Unit V V V Note 1 1 2
NOTE : 1. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
32
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
AC Timing Parameters & Specification
Parameter CL=2 CL=3 Symbol DDR266 Min 12.0 7.5 67.5 45 22.5 22.5 15 15 2*tCK+tRP 1 1 0.45 0.45 2.0 2.0 2.0 2.0 0.55 0.55 8.0 6.0 8.0 6.0 0.6 0.5 0.9 0.4 0.75 0 0.25 0.4 0.25 0.4 0.4 0.2 0.2 0.9 1.3 1.3 2.6 0.8 0.8 1.8 1.0 1.1 0.6 0.6 0.6 1.1 1.1 0.6 1.25 0.5 0.9 0.4 0.75 0 0.25 0.4 0.25 0.4 0.4 0.2 0.2 0.9 1.5 1.5 3.0 1.1 1.1 2.4 1.0

DDR222 Max Min 15.0 9 81 Max
Unit
Note
Clock cycle time Row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Active delay Last data in to Read command Col. address to Col. address dealy Clock high level width Clock low level width Output data access time from CK/CK
tCK tRC tRAS tRCD tRP tRRD tWR tDAL tCDLR tCCD tCH tCL
70,000
54 27 27 15 15 2*tCK+tRP 1 1 0.45 0.45 2.5 2.5 2.5 2.5
70,000
tCK tCK 0.55 0.55 8.0 6.0

tCK tCK 3
CL=2 CL=3 CL=2 CL=3
tAC
DQS output data access time from CK/CK Data storbe edge to output data edge DQS Read Preamble DQS Read Postamble CK to valid DQS-in DQS-in write preamble setup time DQS-in write preamble hold time DQS-in write postamble time DQS-in write preamble time DQS-in high level width DQS-in low level width DQS falling edge to CK set-up time DQS falling edge hold time from CK DQS-in cycle time Address and Control Input setup time Address and Control Input hold time Address and Control input pulse width DQ & DM setup time to DQS DQ & DM hold time to DQS DQ & DM input pulse width DQ and DQS low-impedence time from CK/CK
tDQSCK tDQSQ
8.0 6.0 0.7 1.1 1.1 0.6 1.25
CL=2 CL=3
tRPRE tRPST tDQSS tWPRES tWPREH tWPST tWPRE tDQSH tDQSL tDSS tDSH tDSC tIS tIH tIPW tDS tDH tDIPW tLZ
tCK tCK tCK
tCK 0.6 tCK tCK 0.6 0.6 tCK tCK tCK tCK 1.1 tCK
33

-
2
4
1 1 1 5,6 5,6
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Parameter DQ and DQS high-impedence time from CK/CK Refresh inteval time Mode register set cycle time Power down exit time CKE min. pulse width (high and low pulse width) Auto refresh cycle time Exit self refresh to active command Data hold skew Data hold from DQS to earliest DQ edge 64Mb Symbol tHZ tREF tMRD tPDEX tCKE tARFC tXSR tQHS tQH tHP tHPmintQHS tCLmin or tCHmin 2 1*tCK+tIS 2 80 120 0.75 tHPmintQHS
DDR266 Min Max 6.0 64 2
DDR222 Min Max 7.0 64
Unit
Note
ms tCK
1*tCK+tIS 2 80 120 1.0

tCK
7
Clock half period
tCLmin or tCH min
34
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
NOTES: 1.Input Setup/Hold Slew Rate Derating

Input Setup/Hold Slew Rate
(c)
tIS ) 0
tIH
(V/
)
(
(
) 0
1.0 0.8 0.6
+50 +100 .
(c)
+50 +100
This derating table is used to increase tIS/tIH in the case where the input slew rate is below 1.0V/
2. Minimum 5CLK of tDAL(=tWP +tRP) is required because it need minimum 2 CLKs for tWP and minimum 3 CLKs for tRP.
|
3. tAC(min) value is measured at the high Vdd(1.95V) and cold temperature(-25
|
).
tAC(max) value is measured at the low Vdd(1.7V) and cold temperature(-25 ). tAC is measured in the device with half driver strength(CL=10pF) and under the AC output load condition(fig.2 in next Page). 4. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High-Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 5. I/O Setup/Hold Slew Rate Derating

I/O Setup/Hold Slew Rate
(c)
tDS ( ) 0 +75
tDH
(V/
)
(
) 0
1.0 0.8 0.6
+75 +150 .
(c)
+150
This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 1.0V/ 6. I/O Delta Rise/Fall Rate(1/slew-rate) Derating
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is
(c) (c)
calculated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1=1.0V/ Rate=-0.25 /V. 7. Maximum burst refresh cycle : 8
(c)
(c)
(
/V) 0 0.25
(
) 0
+50 +100
0.5
and slew rate 2=0.8V/
, then the Delta Rise/Fall
35

Delta Rise/Fall Rate
tDS
tDH ( ) 0 +50 +100
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
|
AC Operating Test Conditions (VDD = 1.7V - 1.95V, TA = -25 to 85
Parameter
) Unit VDDQ V V
(c)
Value
AC input levels(Vih/Vil) Input timing measurement reference level Input signal minimum slew rate
0.8
VDDQ / 0.2

0.5
VDDQ 1.0
V/
Output timing measurement reference level Output load condition
0.5
VDDQ
V
See Figure 2
13.9

50" VDDQ, IOH = -0.1 VDDQ , IOL = 0.1

VOH (DC) =0.9 Output 10.6 VOL (DC) =0.1
20
Output
Z0=50!
! ! !
CL
Figure 1. DC Output Load Circuit
Figure 2. AC Output Load Circuit
Parameter Input capacitance (A0 ~ A11, BA0 ~ BA1, CKE, CS, RAS, CAS, WE) Input capacitance(CK, CK) Data & DQS input/output capacitance Input capacitance(DM)
Symbol CIN1 CIN2 COUT CIN3
36
2.0
4.5
2.0
4.5
1.5
3.5
|
Input/Output Capacitance (VDD=1.8V, VDDQ=1.8V, TA=25
, f=1 ) Min 1.5 Max 3.0 Unit
#
20# 10# 5# 2.5
(Full DS) (Half DS) (Quarter DS) (Octant DS)
1.8V
Vtt=0.5
VDDQ
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
AC Overshoot/Undershoot Specification for Address & Control Pins
Parameter Maximum peak Amplitude allowed for overshoot area Maximum peak Amplitude allowed for undershoot area Maximum overshoot area above VDD Maximum undershoot area below VSS Specification 0.9V 0.9V 3V-ns 3V-ns
Maximum Amplitude
Overshoot Area
Volts(V)
VDD VSS Undershoot Area
Maximum Amplitude Time(ns)
Figure 3. AC Overshoot and Undershoot Definition for Address and Control Pins
AC Overshoot/Undershoot Specification for CLK, DQ, DQS and DM Pins
Parameter Maximum peak Amplitude allowed for overshoot area Maximum peak Amplitude allowed for undershoot area Maximum overshoot area above VDDQ Maximum undershoot area below VSSQ Specification 0.9V 0.9V 3V-ns 3V-ns
Maximum Amplitude
Overshoot Area
Volts(V)
VDDQ VSSQ Undershoot Area
Maximum Amplitude Time(ns)
Figure 4. AC Overshoot and Undershoot Definition for CLK, DQ, DQS and DM Pins
37
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Basic timing (Setup, Hold and Access Time @ BL=4, CL=3)
tCH tCL tCH tCL
CK CK CKE CS RAS CAS BA0, BA1 A10/AP ADDR (A0~An) WE
0
1
2
3
4
5
6
tCK
7
8
9
10
tCK
11
12
13
14
15
HIGH tIS tIH
BAa
BAa
BAb
Ra
Ra
Ca
Cb
tRPST
tDQSS
Hi-Z
tDSC tDQSL tWPST
DQS
tRPRE tDQSQ tAC tHZ
Qa0 Qa1 Qa2 Qa3
tDQSH
tWPRES
tWPREH tDS tDH Db0 Db1Db2Db3
DQ DM COMMAND
Active READ
Hi-Z
WRITE
: Don't Care
38
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Multi Bank Interleaving READ (@BL=4, CL=3)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CK CK CKE CS RAS CAS BA0, BA1 A10/AP ADDR (A0~An) WE DQS DQ
HIGH
BAa
BAb
BAa
BAb
Ra
Rb
Ra
Rb
Ca
Cb
tRRD
tCCD
Qa0 Qa1Qa2Qa3Qb0Qb1Qb2Qb3
DM
tRCD
COMMAND
Active
Active
READ
READ
: Don't Care
39
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Multi Bank Interleaving WRITE (@BL=4)
CK CK CKE CS RAS CAS BA0, BA1 A10/AP ADDR (A0~An) WE DQS DQ
Da0 Da1Da2Da3Db0Db1Db2Db3 BAa BAb BAa BAb
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
HIGH
Ra
Ra
Ra
Rb
Ca
Cb
tRRD
tCCD
DM
tRCD
COMMAND
Active
Active
WRITE
WRITE
: Don't Care
40
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Read with Auto Precharge (@BL=8)
0 1 2 3 4 5 6 7 8 9 10
CK CK CKE CS RAS CAS BA0,BA1 A10/AP ADDR (A0~An) WE
HIGH
BAa
BAb
Ra Ca Cb
Auto Precharge start
tRP
DQS (CL=3) DQ (CL=3) DM COMMAND
READ
Note 1
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7
ACTIVE
: Don't Care
NOTE : The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of another activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same bank is illegal.
41
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Write with Auto Precharge (@BL=8)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CK CK CKE CS RAS CAS BA0, BA1 A10/AP ADDR (A0~An) WE
HIGH
BAa
BAa
Ra
Ca
Cb
Auto Precharge start
tWR
tRP
DQS DQ DM COMMAND
WRITE
Note 1
Da0 Da1Da2Da3Da4Da5Da6Da7
Active
: Don't Care
NOTE : 1. The row active command of the precharge bank can be issued after tRP from this point The new read/write command of another activated bank can be issued from this point At burst read/write with auto precharge, CAS interrupt of the same bank is illegal.
42
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Write followed by Precharge (BL=4)
0 1 2 3 4 5 6 7 8 9 10
CK CK CKE CS RAS CAS BA0,BA1 A10/AP ADDR (A0~An) WE
HIGH
BAa
BAa
Ca
tWR
DQS DQ DM
Da0 Da1 Da2 Da3
COMMAND
WRITE
PRE CHARGE : Don't Care
43
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Write Interrupted by Precharge & DM (@BL=8)
0 1 2 3 4 5 6 7 8 9 10
CK CK CKE CS RAS CAS BA0,BA1 A10/AP ADDR (A0~An) WE DQS DQ
HIGH
BAa
BAa
BAb
BAc
Ca
Cb
Cc
Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7
Db0 Db1 Dc0 Dc1 Dc2 Dc3
DM
tWR
tCCD
PRE CHARGE
COMMAND
WRITE
WRITE
WRITE
: Don't Care
44
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Write interrupted by a Read (@BL=8, CL=3)
0 1 2 3 4 5 6 7 8 9 10
CK CK CKE CS RAS CAS BA0,BA1 A10/AP ADDR (A0~An) WE
HIGH
BAa
BAb
Ca
Cb
DQS DQ DM
tWTR Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7
Masked by DM
Qb0 Qb1 Qb2 Qb3
COMMAND
WRITE
READ
: Don't Care
45
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Read interrupted by Precharge (@BL=8)
0 1 2 3 4 5 6 7 8 9 10
CK CK CKE CS
HIGH
RAS
CAS BA0,BA1 A10/AP ADDR (A0~An) WE DQS(CL=3)
2 tCK Valid Ca BAa BAa
DQ(CL=3)
4
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5
DM
PRE CHARGE
COMMAND
READ
: Don't Care
46
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Read Interrupte by a Write & Burst Stop (@BL=8, CL=3)
0 1 2 3 4 5 6 7 8 9 10
CK CK CKE CS
HIGH
RAS
CAS BA0,BA1 A10/AP ADDR (A0~An) WE DQS DQ DM
Burst Stop
Qa0 Qa1 Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb7 Ca Cb BAa BAb
COMMAND
READ
WRITE
: Don't Care
47
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Read Interrupted by a Read (@BL=8, CL=3)
CK CK CKE CS RAS CAS BA0,BA1 A10/AP ADDR (A0~An) WE DQS DQ
Qa0 Qa1 Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb7 Ca Cb BAa BAb
0
1
2
3
4
5
6
7
8
9
10
HIGH
DM
tCCD
COMMAND
READ
READ
: Don't Care
48
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
DM Function (@BL=8) only for write
0 1 2 3 4 5 6 7 8 9 10
CK CK CKE CS
HIGH
RAS CAS BA0,BA1 A10/AP ADDR (A0~An) WE DQS DQ
Da0 Da1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 Ca BAa
DM
COMMAND
WRITE
: Don't Care
49
Rev 0.7
Advanced
64Mb Low Power DDR SDRAM
Mode Register Set
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CK CK CKE
tCK
CS
RAS
CAS
WE
BA0,BA1
A10/AP ADDRESS KEY
ADDR (A0~An) DM
tRP
DQ
High-Z
DQS
High-Z
Precharge Command All Bank
Mode Resister Set Command
Any Command : Don't Care
NOTE : Power & Clock must be stable for 200$
before precharge all banks
50
Rev 0.7

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